A conventional approach to embedded non-volatile memory uses an electrical fuse (hereinafter referred to as eFUSE) that is rapidly becoming unfavorable regarding its area efficiency as the technology continues to scale down. Furthermore the eFUSE does not allow reprogramming data bits, resulting in a one time programmable ROM. High density nonvolatile memory such as a NAND or NOR type flash memory overcomes the problem. However, inherently adding undesirable device structures such as a floating gate or ultra-thick oxide and electrical parasitics (i.e., excessive capacitance, high voltages, typically greater than 5V) are not supported in a high performance logic technology. This requires adding complex additional process elements to be integrated to the high-performance logic technologies, resulting in a high cost.
The prior art uses a charge trap of an N-type MOSFET (NMOS) without using a floating gate, resulting in an embedded Multi-Time-Programmable-Read-Only-Memory (eMTPROM) for a high-performance logic technology. However, the eMTPROM does not have a default state such as 0 that requires programming the bit prior to use. As a result, the prior art does not support the technology for One-Time-Programmable-Read-Only using a charge trap behavior. Even when the technology supports multiple writes, it becomes difficult to use a memory because certain applications require a default state prior to using it. Typically, the number of the eMTPROM programming features is limited to less than 10, and therefore uses one of the limited programming cycles for creating a default state that can make the product less attractive. Furthermore, even when the application does not require a default state, all the bit cells need to be programmed, resulting in a undesired power consumption and a longer programming time.